Buffer circuits (e.g., output buffers and bidirectional buffers) are employed in a variety of electronic devices and applications, particularly networking applications involving high-speed data transfer applications. In order to ensure interoperability between such electronic devices, differential input/output (I/O) buffers are often employed which comply with a set of electrical specifications set forth in one or more standards. One common standard for differential I/O interfaces is the Institute of Electrical and Electronics Engineers (IEEE) 1596.3 standard for low-voltage differential signaling (LVDS). The IEEE 1596.3 standard specifies signaling levels for the high-speed/low-power physical layer interface. It also defines the common mode range of an LVDS buffer. The IEEE 1596.3 standard is set forth in the document IEEE Std. 1596.3, entitled IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherence Interface (SCI), 1996 edition, which is incorporated by reference herein.
In order to satisfy the stringent requirements set forth in such standards, it is necessary to minimize output common mode variation in the buffer circuit. One known approach for reducing output common mode variation in a buffer circuit is to utilize a process, voltage and temperature (PVT) control reference circuit for supplying bias signals to the buffer circuit which track variations in PVT conditions to which the buffer circuit may be subjected. These bias signals can be replicated using conventional replica bias circuitry (e.g., current mirrors, etc.) so that a single control reference circuit can support several buffer circuits. This approach, however, generally does not provide sufficient control of the output common mode variation as may be required to meet a particular standard due, at least in part, to direct current (DC) offsets in operational amplifiers (opamps) used in the control reference circuit and/or buffer circuit, relative voltage (current-resistance (IR)) drops between the PVT control reference circuit and the buffer circuit, and/or device mismatches between the replica bias circuitry and the buffer circuit. Each of these factors contributes to an overall inaccuracy of the control reference circuit and hence reduces an effectiveness of the control reference circuit in controlling the output common mode voltage of the buffer circuit.
Another known approach for reducing output common mode variation in a buffer circuit is to employ current referencing in conjunction with a common mode feedback scheme using an opamp. This approach provides a more accurate mechanism for controlling output common mode variation in the buffer circuit compared to the PVT reference generator approach previously described. However, this circuit arrangement requires the use of an opamp to implement the common mode feedback scheme. The use of an opamp and accompanying compensation circuitry required by the opamp significantly increases a chip area of the buffer circuit. Moreover, a current reference circuit is typically required for each buffer circuit in order to guarantee the accuracy necessary to meet certain standards (e.g., IEEE 1596.3). When the buffer circuit employing common mode feedback is used in conjunction with a PVT reference circuit for supplying bias current thereto, the number of buffer circuits that can be driven by a single PVT reference circuit is significantly reduced. Therefore, the total number of PVT reference circuits required in a given IC undesirably increases, especially in integrated circuits utilizing a large number of buffer circuits. This substantially increases a cost of the IC.
Accordingly, there exists a need for an improved differential buffer circuit that has reduced output common mode variation and yet does not suffer from one or more of the problems exhibited by conventional buffer circuits.